1. Field of the Invention
This invention generally relates to semiconductor devices and fabrication methods of the same, and more particularly, to a semiconductor device in which a GaN-based semiconductor layer is selectively formed and a fabrication method of the same.
2. Description of the Related Art
Semiconductor devices having a GaN-based semiconductor or SiC-based semiconductor are used as a power device that operates at high frequencies and high power. As a semiconductor device having the GaN-based semiconductor or SiC-based semiconductor, FET such as HEMT (High Electron Mobility Transistor) or the like, IGBT (Insulated Gate Bipolar Transistor), and MOSFET (Metal Oxide Semiconductor FET) are well known. The GaN-based semiconductor is a single crystal or mixed crystal composed of, for example, at least one of GaN, AlN, and InN.
Here, a description will be given of a process of providing an opening portion in the GaN-based semiconductor device (hereinafter, referred to as conventional technique 1), in fabricating the semiconductor device having a vertical structure with the use of the GaN-based semiconductor. FIG. 1A through FIG. 1C are cross-sectional views of a fabrication process of the conventional technique 1. Referring to FIG. 1A, a GaN-based semiconductor layer 108, which includes a drift layer 102, an electron control layer 104, and a contact layer 106, is formed on a substrate 100.
Referring to FIG. 1B, a photo resist 120 having an opening in a given region is formed. Referring to FIG. 1C, the contact layer 106 is dry etched by the use of Cl2 with the photo resist 102 that serves as a mask, so as to form an opening portion in the contact layer 106. A gate electrode 112 is provided in the opening portion and a source electrode 110 is provided on the contact layer 106. In this manner, the opening portion is formed by etching the GaN-based semiconductor layer 108.
Also, as another technique of forming the GaN-based semiconductor layer, the following arts (hereinafter, referred to as conventional technique 2) are disclosed. According to Japanese Patent Application Publication No. 11-251253, an underlying layer fabricated of the GaN-based semiconductor is formed on the substrate, which is not the GaN-based semiconductor so as to partially provide a protection film on the underlying layer. This discloses the technique of forming the GaN-based semiconductor layer on the underlying layer without the protection film. Japanese Patent Application Publication No. 2000-349338 discloses a technique of forming the mask in strips and providing the GaN-based semiconductor layer to cover the mask.
In the conventional technique 2, however, if the GaN-based semiconductor having a thick drift layer is formed on a sapphire substrate or SiC substrate, for example, a distortion or warp occurs on the substrate. This causes a crack in the substrate or the GaN-based semiconductor layer. Besides, in the fabrication process of the semiconductor device, accuracy in alignment is degraded in the lithography process.
In addition, in the conventional technique 1, while the opening portion is being formed in the GaN-based semiconductor layer, damage is introduced into side walls of the opening portion in the contact layer 106 or a bottom of the opening portion of the electron control layer 104. In a conductive region of the GaN-based semiconductor layer, this damage generates a trap level on a surface of the semiconductor or in the semiconductor, and inactivated carriers and reduces concentrations of electrons and holes. Also, in an insulating region of the GaN-based semiconductor layer, the trap level generated by the damage causes leakage current to flow. With these reasons, the electric characteristics of the semiconductor device will be deteriorated.